Generally, a liquid crystal display LCD device has liquid crystal cells, which are arranged in a liquid crystal display panel in a matrix shape. The liquid crystal cells control light transmittance in accordance with a video signal, thereby displaying a picture.
A thin film transistor (hereinafter, referred to as ‘TFT’) is used as a switching device for independently supplying a video signal in each of the liquid crystal cells. Amorphous silicon or poly silicon is used for a semiconductor layer of such a TFT. When using poly silicon, which has a charge mobility 100 times faster than amorphous silicon, a drive circuit with a high response speed can be embedded in the liquid crystal display panel.
FIG. 1 briefly illustrates a TFT substrate of a related art poly liquid crystal display panel where a drive circuit is embedded.
A poly silicon TFT substrate shown in FIG. 1 includes a picture display area 7 where a TFT 30 and a pixel electrode 22 are formed at each pixel area defined by the crossing of a gate line 2 and the data line 4; a data driver 5 for driving the data line 4 of the picture display area 7; and a gate driver 3 for driving the gate line 2 of the picture display area 7.
The picture display area 7 includes the TFT 30 and the pixel electrode 22 which are formed at each pixel area that is defined by the cross of a plurality of gate lines 2 and a plurality of data lines 4. The TFT 30 charges a video signal from the data line 4 in the pixel electrode 22 in response to a scan signal of the gate line 2. The pixel electrode 22 charged with the video signal generates a potential difference with a common electrode of a color filter substrate which faces a TFT substrate with liquid crystal therebetween, thereby making liquid crystal molecules rotate by dielectric anisotropy in accordance with the potential difference. The light transmittance is changed in accordance with the degree of rotation of the liquid crystal molecules, thereby realizing a gray level.
The gate driver 3 sequentially drives the gate line 2.
The data driver 5 supplies a video signal to the data line 4 whenever the gate line 2 is driven.
FIG. 2 is a plane view illustrating an enlarged pixel area included in a picture display area 7 of the poly silicon TFT substrate shown in FIG. 1, and FIG. 3 is a sectional diagram illustrating a pixel area of the TFT substrate shown in FIG. 2, taken along the line I-I′.
The TFT substrate shown in FIGS. 2 and 3 includes a TFT 30 connected to the gate line 2 and the data line 4, and a pixel electrode 22 connected to the TFT 30. The TFT 30 is an NMOS TFT or a PMOS TFT, but only the NMOS TFT is explained below.
The TFT 30 includes a gate electrode 6 connected to the gate line 2; a source electrode included in the data line 4; and a drain electrode 10 connected to the pixel electrode 22 through a pixel contact hole 20 that penetrates a passivation film. The gate electrode 6 is formed to overlap a channel area 14C of a semiconductor layer 14 which is formed on a buffer film 12 with a gate insulating film 16 therebetween. The source electrode and the drain electrode 10 are formed on an interlayer insulating film 26. The interlayer insulating film 26 is also between the gate electrode 6 and the source and drain electrodes. The source electrode and the drain electrode 10 are respectively connected to a source area 14S and a drain area 14D of the semiconductor layer 14 into which n+ impurities are injected through a source contact hole 24S and a drain contact hole 24D which penetrates the interlayer insulating film 26 and the gate insulating film 16.
The picture display area 7 of the poly silicon TFT substrate is formed by six mask processes as below.
Specifically, in a first mask process, a buffer film 12 is formed on a lower substrate 1 and the semiconductor layer 14 is formed thereon. The semiconductor layer 14 is formed by patterning a poly silicon layer with a photolithography process and an etching process using a first mask after depositing amorphous silicon on the buffer film 12 and crystallizing the deposited amorphous silicon with a laser to form the poly silicon.
In a second mask process, the gate insulating film 16 is formed on the buffer film 12 where the semiconductor layer 14 is formed, and the gate line 2 and the gate electrode 6 are formed thereon. The gate electrode 6 is used as a mask to inject n+ impurities into a non-overlapping area of the semiconductor layer 14, thereby forming the source area 14S and the drain area 14D of the semiconductor layer 14.
In a third mask process, the interlayer insulating film 26 is formed on the gate insulating film 16 where the gate line 2 and the gate electrode 6 are formed, and the source contact hole 24S and the drain contact hole 24D are formed to penetrate the interlayer insulating film 26 and the gate insulating film 16.
In a fourth mask process, the drain electrode 10 and the data line 4 including the source electrode are formed on the interlayer insulating film 26.
In a fifth mask process, the passivation film 18 is formed on the interlayer insulating film 26 where the data line 4 and the drain electrode 10 are formed, and a pixel contact hole 20 is formed to penetrate the passivation film 18 to expose the drain electrode 10.
In a sixth mask process, a transparent pixel electrode 22 connected to the drain electrode 10 through the pixel contact hole 20 is formed on the passivation film 18.
In this way, the picture display area 7 of the related art poly silicon TFT substrate is formed by the six mask processes. However, the fabricating process is complicated because each mask process includes a number of processes, for example: a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photo resist peeling process, an inspection process and so on.
Further, the related art poly silicon TFT substrate is used to form a CMOS TFT if a storage capacitor is formed in the picture display area 7 and the gate driver 3 and data driver 5 are formed. This increases the number of processes to nine mask processes, which further complicates the fabricating process. Accordingly, a method that reduces the number of mask processes of the poly silicon TFT substrate is desirable, at least for reasons of cost among others.